1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection control circuit and system, and more particularly, to an ESD protection control circuit and system capable of improving ESD protection on an output pad of an integrated circuit.
2. Description of the Prior Art
With advancement in semiconductor process technology, the dimension of circuit elements shrinks to a submicron level, which increases performance and operation speed of integrated circuits (ICs). Reliability issues also become significant with decreasing element dimensions. Among these issues, electrostatic discharge (ESD) is one of the most important issues to be dealt with. Since the circuit elements in advanced processes have smaller dimensions, the ESD tolerance capability of the circuit elements becomes worse, while the quantity of environmental static electricity still remains. Therefore, the circuit elements may be damaged by ESD more easily.
There are two conventional circuit designs for ESD protection on an output pad. One is the self-protection method, and the other applies an external ESD protection cell to assist in ESD protection. Please refer to FIG. 1, which is a schematic diagram of a circuit structure of an output pad in an IC with self-protection. FIG. 1 illustrates an open drain circuit structure, which includes an output pad LX, an output transistor 100 and a previous stage 102. As the open drain circuit, the output transistor 100 is an N-type metal oxide semiconductor (NMOS) transistor with its drain terminal coupled to the output pad LX. The gate terminal of the output transistor 100 is coupled to the previous stage 102, for receiving control signals from the previous stage 102. The previous stage 102 includes an inverter 104 to output the control signals to drive the output transistor 100. In the circuit structure shown in FIG. 1, the output transistor 100 should follow a layout rule with higher ESD tolerance capability, where the distance from contact to poly may be larger and/or a salicide block (SAB) layer is disposed. In this manner, the output transistor 100 can bear higher ESD stress without additional ESD protection cells. However, the layout rule with higher ESD tolerance capability always requires a larger area and is thereby accompanied by poor performance. Especially when the output transistor 100 is a power transistor with a larger dimension, the layout area may increase much more in order to meet the layout rule for ESD protection.
Please refer to FIG. 2, which is a schematic diagram of a circuit structure of an output pad in an IC implemented with an external ESD protection cell 200. The circuit structure shown in FIG. 2 is similar to the circuit structure shown in FIG. 1, where the same circuit elements are denoted by the same symbols. The main difference thereof is that FIG. 2 further includes the ESD protection cell 200, which is connected to the output transistor 100 in parallel, for passing through ESD currents when the ESD currents are inputted from the output pad LX. However, there is a parasitic capacitance Cgd between the gate terminal and drain terminal of the output transistor 100. When an ESD voltage arrives at the output pad LX, the ESD voltage may be coupled to the gate terminal to turn on the output transistor 100 before the ESD protection cell 200 is turned on. If the layout of the output transistor 100 does not meet the rule for high ESD tolerance, the output transistor 100 may easily be burnt by ESD currents. Especially when the output transistor 100 is a power transistor with a larger dimension, the parasitic capacitance Cgd may be larger and thereby couple the ESD voltage signal to the gate terminal more easily.
As can be seen, the conventional ESD protection techniques are not satisfactory. Thus, there is a need to provide another circuit structure to achieve better ESD protection.